Abstract
Approximate computing is an emerging approach for designing high performance and low power arithmetic circuits. The logarithmic multiplier (LM) converts multiplication into addition and has inherent approximate characteristics. A method combining the Mitchell's approximation and a dynamic range operand truncation scheme is proposed in this paper to design non-iterative and iterative approximate LMs. The accuracy and the circuit requirements of these designs are assessed to select the best approximate scheme according to different metrics. Compared with conventional non-iterative and iterative 16-bit LMs with exact operands, the normalized mean error distance (NMED) of the best proposed approximate non-iterative and iterative LMs is decreased up to 24.1% and 18.5%, respectively, while the power-delay product (PDP) is decreased up to 51.7% and 45.3%, respectively. Case studies for two error-tolerant applications show the validity of the proposed approximate LMs.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
