Design of approximate Redundant Binary multipliers

Abstract

Approximate or inexact computing is an attractive design methodology for low power design and is achieved by relaxing the requirement of accuracy. This paper proposes the first approximate design of Redundant Binary (RB) multipliers. An approximate Booth encoder and an approximate RB compressor are proposed and analyzed. RB multipliers are proposed based on the proposed approximate Booth encoder and approximate RB compressor. A regular RB partial product array is also applied in the approximate RB multiplier by eliminating the last Error Correcting Word (ECW). The error analysis is performed by considering the approximate factor as related to the inexact bit width of the RB multipliers. Simulation results for delay, area and power consumption at 45nm CMOS technology are provided. The proposed designs are compared with previous approximate Normal Binary (NB) Booth multipliers; the comparison results show that the proposed designs are better than existing approximate NB Booth multipliers when considering both the Power-Delay Product (PDP) and the Normalized Mean Error Distance (NMED).