Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Abstract

Redundant binary (RB) representation possesses some figures of merit as an internal format for the design of datapath components due to its carry-free property and avoidance of sign extension. Being a non-classical representation, its worth in meeting conflicting VLSI goals has not been fully evaluated. This chapter presents a structural and systematic approach to the design and analysis of different Booth multipliers in RB representation by decomposing them into several key building blocks. The design considerations on each of these generic constituent modules and their logic circuits are first discussed qualitatively and independently before they are selectively fused into different configurations of Booth multipliers. To unify the heterogeneous fabrics designed with different coding formats together, simple anterior and posterior converters are derived for their interfacing. Altogether 21 different RB multiplier architectures have been constructed with various configurations of partial product encoding, generation and reduction to analyze their design trade-offs in terms of area, delay, and energy consumption. These multipliers have been implemented and compared for various VLSI metrics with six commonly used operand lengths varying from 8 bits to 64 bits. The intriguing augmentation and restriction between different architectural modules inferred from this comparative study are inspirational to innovative RB multiplier design. It is shown that a large design space can be explored from sensible topological combinations of different constituent modules of RB multiplier architecture for the desirable performance characteristics.