Design of a ternary QCA multiplier and multiplexer: a model-based approach

Abstract

A ternary arithmetic and logic unit is a digital circuit that performs arithmetic and logic operations in computer circuits such as central processing units of computers. Ternary multiplication is one of the most complicated operations in processors. Multipliers are the most important components of ternary arithmetic and logic units and a multiplexer is a significant building block for logical design purposes. The current study was undertaken to design a ternary multiplier and a multiplexer based on the comprehensive ternary QCA model which has been implemented in our previously proposed software tool (TQCAsim). In order to meet this aim, the ternary multiplier first was designed using a 3 × 1 multiplexer and then a regular multiplier was designed and investigated. To evaluate the designed circuits, the proposed multipliers were simulated in TQCAsim. Effective factors such as area occupation, energy consumption and cost were investigated in the proposed circuits and the designs were compared.