Design of a Single-Ended 8T SRAM Cell for Low Power Applications

Abstract

This paper presents a single-ended eight-transistor (8T) static random-access memory (SRAM). The proposed cell achieves enhanced write ability by weakening the pull up transistor during write ‘0’. Feedback loop cutting approach is employed for successfulwrite ‘1’ operation. Unlike the conventional 6T cell, proposed 8T cell employs separate transistors for read and write operations to eliminate conflicting design requirement on access transistor. Simulation is done on 180 nm CMOS technology on Cadence. Write static noise margin (WSNM) of the proposed SRAM cell is 9% largerthan that of the conventional 6T cell at 400 mV. The proposed cell consumesless leakage power 0.94x as that of the conventional 6T cell at 400 mV.