Abstract

In this work the design of a constant fraction discriminator (CFD) to be used in the VFAT3 chip for the read-out of the triple-GEM detectors of the CMS experiment, is described. A prototype chip containing 8 CFDs was implemented using 130 nm CMOS technology and test results are shown.

Highlights

  • - A micro-TCA based data acquisition system for the Triple-GEM detectors for the upgrade of the CMS forward muon spectrometer T

  • The detector signal is convolved with the expected transfer function of the front-end amplifier of VFAT3 chip and the time resolution and latency for various VFAT3 peaking times are computed using the constant fraction discriminator (CFD) and the time-over-threshold (TOT) techniques

  • The input signals are sent in parallel to an arming circuitry, in order to enable the CFD output only when the input signal is larger than the programmed threshold provided by a global 8-bit digital-to-analog-converter (DAC)

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Summary

Simulation

The time resolution, which is an important parameter for the use of the GEM detectors at the first CMS trigger level, has been studied with Monte Carlo simulations. The simulations are based on the GARFIELD [2] software to compute the CMS triple-GEM signals, taking into account the ionization statistics, the charge drift and amplification processes inside the gas volume of the detector [3]. The detector signal is convolved with the expected transfer function of the front-end amplifier of VFAT3 chip and the time resolution (figure 3) and latency (figure 4) for various VFAT3 peaking times are computed using the constant fraction discriminator (CFD) and the time-over-threshold (TOT) techniques. The simulation study showed that it was possible to extend the VFAT3 front-end shaping time in order to fully integrate the GEM detector signal charge and avoid ballistic deficit and that the most efficient method, in terms of combined time resolution and latency, is the CFD method. Technique, for a peaking time of 50 ns and a gas mixture of Ar/CO2/CF4 of 45:15:40, the simulated time resolution is 4.98 ± 0.16 ns with a total latency of 100 ± 5 ns

Principle of operation
Architecture
Prototypes
Test results
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