Abstract
This paper presents a 10b SAR ADC for biomedical applications. The Analog-to-digital converter (ADC) is powered by a single supply voltage of 1V. To reduce power, dynamic comparator circuit is used. The use of binary weighted capacitive Digital to Analog converter (CDAC) can also bring power reduction. The successive approximation algorithm performs the analog to digital conversion over multiple clock cycle periods by exploiting the knowledge of previously determined bits to determine the next significant bit. This method aims to reduce the circuit complexity and power consumption using a low conversion rate by allowing one clock period per bit. The 10b Successive approximation register ADC (SAR ADC) was designed in 0.18μm CMOS technology. It consumes 4.5μW power at 1V and area occupied is 0.04mm2.
Published Version
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