Design model for minority-carrier well-type guard-rings in CMOS circuits

Ming-Jer Chen Ming-Jer Chen,Ping-Nan Tseng Ping-Nan Tseng,Nun-Sian Tsai Nun-Sian Tsai,Ching-Yuan Wu Ching-Yuan Wu,Chih-Yao Huang Chih-Yao Huang

doi:10.1109/cicc.1991.164068

Design model for minority-carrier well-type guard-rings in CMOS circuits

Ming-Jer Chen Ming-Jer Chen, Ping-Nan Tseng Ping-Nan Tseng + Show 3 more

https://doi.org/10.1109/cicc.1991.164068

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Publication Date: May 12, 1991

Citations: 4

Affiliation: National Yang Ming Chiao Tung University, Taiwan Semiconductor Manufacturing Company (Taiwan)

#Guard Ring Width #Two-dimensional Numerical Simulation + Show 8 more

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Abstract

A novel analytic model for minority-carrier well-type guard ring design has been developed for CMOS circuits. This model, expressed as a function of epi-layer thickness, well junction depth, and guard ring width, has been verified by two-dimensional numerical simulation as well as by experimental data. Also, the model has been confirmed to be valid by temperature measurements. The effect of a floating well-type guard ring has been addressed. >

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