Design Method of Build-in Test Equipment Interface in FPGA System Based on JTAG

Abstract

Data transmission in typical Build-in Test Equipment (BITE) with FPGA system is based on FPGA’s input and/or output (I/O) pins. It occupies some IO resource, and cannot be used in having been designed system whose hardware change is not allowed. FPGA system usually has a JTAG (Joint Test Action Group) interface, which is not used when the system working. Therefore, we present a BITE data transmission interface design method using the idle JTAG interface in FPGA system. Principle and design method is introduced in detail, and a design demo is given. Experiment based on the design is conducted; results verify the effectiveness of the method.