Design of Generic Debug Infrastructure of SoC

Abstract

Implementing debug logic in the SoC plays an important role before the product goes on sale. There are some design flaws and verification errors that can be found with advanced verification techniques. Because of this, it is important to add debug logic to the SoC to help with debugging. Debugging is the process of finding and fixing system errors. When silicon came out, the visibility was greatly reduced. As a result, the debug component becomes important. This task is intended to implement debug logic in the SoC. The debug infrastructure consists of debug hosts like JTAG input/output pins (TDI, TMS, TCK, TRST, TDO), protocol conversions like JTAG2APB/JTAG2AHB, and debug targets like cores. Many such protocols are needed in the VLSI industry to compete with the rapid growth of IC technology. In this work, we used the JTAG (Joint Test Action Group) protocol as the debug input pins to send the data and address to the debug target. The APB (Advanced Peripheral Bus) and AHB (Advanced High-performance Bus) protocols are used to communicate and program the debug components. JTAG2APB and JTAG2AHB act as a bridge to convert the serial communication protocol to a parallel communication protocol. As a result, we can communicate and debug any of the core. This method saves a lot of complexity in the SoC.