Design Matrix Analysis for Capacitive Interpolation Flash ADC

Abstract

Flash ADC with interpolation featuring high sampling rate has been widely used in high-speed electronics systems. Unfortunately, practical ADC design is an extremely challenging task that has been largely experience-based and trial-and-error oriented. This paper presents a new quantitative ADC design matrix analysis method for interpolated flash ADCs. The new ADC design matrix establishes a quantitative mapping between key specifications of flash ADC chips and various factors at structures, block circuits, devices and technology levels. It depicts the quantitative influences of design parameters, such as, interpolation factor, number of stages, pre-amplifier bandwidth, loading effects, parasitic transistor capacitance, transistor size and electrical parameters on the overall ADC performance including total bandwidth and sampling speed. This new quantitative design matrix aims to provide a practical design methodology for fast and relatively accurate flash ADC design to achieve reasonable whole-chip ADC optimization with a focus on sampling speed and resolution bit analysis in examples. This ADC design matrix was validated by designs of 4-bit flash ADCs in commercial 0.13 μm and 90 nm CMOS technologies.