Design insights into a junctionless nanosheet FET (JL-NSFET) for switching and Analog/RF applications: Device to circuit level assessment

Abstract

- The advent in semiconductor technology paved the way for electronic industry to place in front row. The nanosheet (NS) device is a type gate all around (GAA) architecture provides an excellent gate electrostatic to suppress the short channel effects (SCEs) and scale it further below sub-7nm technology node. This paper provides a complete design insight from device to circuit of a two sheet NSFET with geometrical variations. All digital and analog/RF parameters are extracted and analyzed based on gate length (LG), sheet thickness (TNS), sheet width (WNS), and spacer material variations. As LG is varied from 8 nm to 12 nm, ION/IOFF is enhanced from 0.249 × 108 to 2.86 × 108 due to improved gate control over the channel region which is also reflected in DIBL to 40.82 % whereas, at lower LG analog/RF metrics are better. The TNS play a vital role in device characteristics, as TNS decreases the chance of interaction of electric field from source to drain decreases owing to full volume conduction and thereby ameliorated performance of JL NSFET. As TNS is varied from 7 nm to 5 nm, all electrical characteristics are improved and analog/RF parameters gm, Av, fT, TFP and GTFP are improved to 10.3 %, 18.4 %, 12.1 % 18.5 % and 54.04 %, respectively. Increase in WNS from 10 nm to 20 nm results into increased effective width of a device, it leads to higher ION current which further impacts on electrical and analog/RF parameters. The DIBL, gm, fT, GFP, TFP and GTFP are enhanced to 63.7 %, 37.9 %, 34.9 %, 9.7 %, 33.5 %, 9.1 %, respectively. The spacer materials are varying from Al2O3 (k = 18), HfO2 (k = 22), ZrO2 (k = 25) to TiO2 (k = 44), the electrical characteristics are better at higher-k whereas analog/RF performances are superior at lower-k. Further, digital circuit elements NOT, NAND and NOR gates are designed, simulated and the delays are examined as 4.25ps, 6.45ps and 5.12ps, respectively. The NML and NMH of NOT gate are noticed as 295 mV and 280 mV at 0.7 V of supply voltage. Furthermore, a common source (CS) amplifier is also simulated and gain of 3.3 is noticed. The aforementioned analysis revels the JL NSFET is best suitable candidate for future nanoscale applications.