Design implications of extremely restricted patterning

Abstract

Escalating manufacturing cost and complexity is challenging the premise of affordable scaling. With lithography accounting for a large fraction of wafer costs, researchers are actively exploring several cost-effective alternative lithographic techniques, such as directed self-assembly, self-aligned multiple patterning, etc. However, most of the alternative lithographic techniques are restrictive, and it is important to understand the impact of such pattering restrictions on system-on-chip (SoC) design. To this end, we artificially restricted all layers in a 14 nm process to be pure gratings and observed that the pure gratings approach results in an inefficient SoC design with several process integration concerns. To come up with a technology definition that is mindful of designer requirements, it is essential to undertake a holistic design technology co-optimization (DTCO) considering several SoC design elements, such as standard cell logic, static random access memory bitcells, analog blocks, and physical synthesis. Our DTCO on the IBM 14 nm process with additional 10- and 7-nm node-like pattern restrictions leads us to converge on a set of critical pattern constructs that are required for an efficient and affordable SoC design.