Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory

Abstract

Problem statement: As technology scales down, the integration density of transistors increases and most of the power is dissipated as le akage. Leakage power reduction is achieved in Stati c Random Access Memory (SRAM) cells by increasing the source voltage (source biasing) of the SRAM array. Another promising issue in nanoscaled devices is the process parameter variations. Due to these variations, higher source voltage causes t he data stored in the cells of the SRAM array to fl ip (weak cell) in the standby mode resulting in hold f ailure. The weak cells identified are replaced usin g redundant columns. Maximum source voltage that can be applied to reduce the leakage power without any failure depends on the number of redundant colu mns available to repair the weak cells. Approach: This study proposes a novel Design For Test (DFT) t echnique to reduce the number of March tests, thus reducing the test time using a source bias (V SB ) predictor. In the proposed method, V SB predictor predicts the initial source bias voltage to be appl ied to the SRAM array. The proposed DFT verified by designing an 8◊16 SRAM array in 90 nm technology. March algorithm was used to identify the weak cells and predict the maximum source voltage from '0' mV. This process was run large number of March tests consuming more test time. Results and discussion: The predicted V SB helps to make a fast convergence of maximum V SB to be applied, which will improve the speed perfor mance of the adaptive source bias and saves the test time by 60 %.