Design exploration for network on chip based FPGAs: 2D and 3D tiles to router interface

Abstract

Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. However, one drawback of using NoC is that increasing its router ports affects the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach, an efficient way has to be found to interface a large number of blocks without increasing NoC router ports. In this paper, a concentrator module or a Codec, is used to connect between routers and multiple Tiles (FPGA basic building block). Usage of Codec reduces the effect of increasing tile count on the area, power and frequency of the FPGA routing network. Different 2D and 3D network configurations are compared to investigate the effects of adding the Codec module.