Advanced Memory Management Unit for 3-D Network on Chip

Abstract

Future generation chip multiprocessor (CMP) contains thousands of cores to increase performance the system. Network on Chip (NoC) is new paradigm for the intercommunication of System on Chip (SoC). 3-D NoC is the new way of improvement in NoC fabric to achieve high performance. One of major drawbacks of NoC is memory unit and it is proportionally increases in 3-D NoC. A first in first out (FIFO) is conventionally placed in NoC router to store data packet temporarily. The memory is critical issue for NoC based SoC because of size and cost of device. Advanced memory architecture presented to optimize the performance of NoC router. This paper proposes a random access memory (RAM), which is a bridge between input ports and crossbar switch. This technique is simulated in Xilinx 14.7 ISE and implemented in Vertex-6 FPGA device.