Design Consideration of Bulk FinFETs Devices With $\hbox{\rm n}^{+}\hbox{/}^{}\hbox{\rm p}^{+}\hbox{/}^{}\hbox{\rm n}^{{+}}$ Gate and $\hbox{\rm p}^{+}\hbox{/}^{}\hbox{\rm n}^{{+}}$ Gate for Sub-50-nm DRAM Cell Transistors

Abstract

In this paper, design considerations for the n+/p+/n+ gate bulk FinFET in sub-50-nm technology nodes is extensively studied through 3D device simulation. For the comparison of electrical characteristics of n+/p+/n+ gate bulk FinFET, the electrical characteristics of p+/n+ gate bulk FinFET were also studied. The electrical characteristics of devices with different n+ gate lengths (L s) and fin body widths ( W fin) were compared in terms of threshold voltage ( V th), on -current (I ON), off -state current (I OFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL). In this study, with a limit of gate length ( L g les 50 nm) and a fin body width ( W fin les 30 nm), bulk FinFETs were designed to achieve an off-current less than 1 fA. Two-nanometer-thick SiO2 layers were inserted between an n+ gate and a p+ gate of the device with n+/p+/n+ gate. Then, the electrical characteristics of the device were studied. Specifically, the source/drain to gate overlap length (L ov)s were changed for both the bulk FinFETs with n+/p+/n+ gate and the device with a p+ gate. Then, the electrical characteristics of both devices were compared.