Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors

Abstract

For given gate lengths (Lg≤40 nm) and fin body widths (Wfin≤30 nm), p+/n+ and n+/p+/n+ gate bulk fin field effect transistors (FinFETs) with a source/drain to gate underlap were designed to overcome the challenges in a sub-40 nm technology node. Their characteristics were compared with those of p+ gate bulk FinFETs through three-dimensional device simulation. We concentrated on device characteristics, such as on state current (Ion), off state current (Ioff), subthreshold swing (SS), and drain-induced barrier lowering (DIBL), by controlling the overlap length of the source/drain-to-gate electrode and fin body width (Wfin). We also investigated the characteristics of p+/n+ and n+/p+/n+ gate bulk FinFETs with various n+ gate lengths (Ls's).