Design and VLSI Implementation of Efficient Systolic Array Architectures for High-Speed Digital Signal Processing Applications

Abstract

In this paper, we present a class of systolic array architectures (SAAs) that can be efficiently used to implement many computationally intensive DSP functions. A salient feature of the proposed architectures is that depending on an application, it is possible to adapt an SAA design intended for particular DSP function and arithmetic type in order to perform other DSP function and arithmetic operation with a minimal hardware modification involving suitable interconnection of the basic building blocks: the inner-product-step-processor (IPSP) cells. This facilitates the process of automatic selection of a particular SAA design depending on the algorithm description of a given DSP function. Furthermore, the proposed SAAs either totally eliminate or minimize the use of separate adder modules which are normally used along with multiplier units in order to perform the inner-product-step computations involved in 1- and 2-dimensional DSP functions. Finally, the use of the proposed schemes results in reductions in the computation time, the area, and the number of cell types thus making them highly attractive for VLSI implementation.