Systolic array architectures for computation of the discrete wavelet transform

Abstract

For computation of the 1-D and 2-D discrete wavelet transforms (DWTs), this paper proposes systolic array architectures that are independent of the sequence size and the nature of wavelet. The proposed systolic arrays for the 1-D DWT consist of L processing element (PE) arrays, where L denotes the number of levels of the architectures. The proposed PE array computes only the product terms that are required for further computation at higher levels, and the outputs of lowpass and highpass filters are computed by a single architecture in alternate clock cycles. Note that the proposed architectures, suitable for hardware implementation, do not require extra control units such as complex control unit and global interconnection whereas the existing architectures need them. The proposed systolic array for the 2-D DWT consist of a small memory unit and a number of systolic array architectures, each of which computes the 1-D DWT. The required time and hardware cost for computation of the DWT using the proposed systolic arrays are comparable to those of the existing architectures.