Systolic array architecture implementation of parasitic-insensitive switched-capacitor filters

Abstract

A systematic procedure is developed for implementing switched-capacitor filters in systolic array architecture. The most complete signal flow graphs that satisfy the conditions of a systolic array, and also the general first-and second-order transfer functions, are considered. A step-by-step reduction procedure is then developed for the second-order signal flow graphs that yield structures which can be implemented with a minimal amount of hardware in LSI/VLSI technology. Implementation of switched-capacitor filters using these reduced signal flow graphs is discussed. Some structures that are not strictly systolic are also considered for second-order filters. Generation of parasitic-insensitive second-order switched-capacitor filters using systolic array architecture are, however, treated in detail, both for biphase (two-phase) and for four-phase clocking schemes. Guidelines for minimising the total capacitance are given and the sensitivity characteristics are provided. Systolic array architecture realisation of a higher-order switched-capacitor filter is illustrated. Results obtained from a bandpass switched-capacitor filter, implemented on a VLSI workstation (SUN) supporting a 3 μm CMOS technology, are reported. Simulation results for a fourth-order filter realised using systolic array architecture are provided.