Design and VLSI architecture and implementation of wave digital filters using short signed digit coefficients

Abstract

The good dynamic range, low round-off noise characteristics and low coefficient sensitivity of wave digital filters make them suitable for realisations with short coefficient word-lengths. The authors discuss the design and implementation of a wave digital architecture using short signed digit coefficient ranges. The fundamental processing block employed in the implementation is the two port adaptor. Restricting the coefficients to this particular form reduces the number of levels of addition required in its implementation. Both the algorithmic and architectural aspects of this are considered. The resultant hardware increases the upper operating frequency, or sample rate, of the realisation, but at the expense of restrictions in the range of filter specifications that can be met. Hardware for a low latency, high clock rate adaptor is developed and cast into a form suited to VLSI implementation. A demonstrator for the concept has been designed and successfully fabricated in 1 /spl mu/m standard-cell CMOS technology. It is a programmable, cascadable device that may be applied to all standard filter types. The chip has a die area of 12.7 mm/sup 2/ and has been successfully tested to a clock rate of 30 MHz, which is twice the maximum filter sample rate.