Abstract
The ferroelectric transistor (FeFET) provides unique characteristics of memory circuits due to its hysteresis effects. This paper examines the design considerations of a 1T-1C dynamic random-access memory (DRAM) cell using a ferroelectric transistor. The research investigates the effects of the FeFET on the DRAM cell while modifying design parameters which are controlled by the circuit designer. Parameters include channel width and length and write-word-line (WWL) voltage. Experimental data will be taken for different circuit configurations. Comparisons will be made to similar circuits that utilize only metal-oxide-semiconductor field effect transistors (MOSFETs).
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