Design and simulation of low power dynamic logic circuit using footed diode domino logic

Abstract

In this paper, we proposed a new technique to reduce power dissipation for domino logic circuits. In this proposed circuit we put a diode on the foot of domino logic circuit which results in power reduction as compared to reported and conventional domino logic. We are using NMOS as a diode and due to this extra diode (NMOS), in precharge period leakage current reduce due to stacking effect. For simulation we are using cadence spectre tool at 180nm CMOS technology and comparison between conventional, reported & proposed logic styles has been done. The result of simulation shows an improvement of 72% and 41% power as compared to the standard conventional domino logic & pseudo dynamic buffer based domino logic.