Design and Simulation of a Small Power Two-Bit MC Circuit via Full Adder Logic

Abstract

In Very Large-Scale Integration (VLSI) systems, a magnitude comparator (MC) is a component of Arithmetic Logic Unit (ALU) used to make binary decisions. Recent technologies demand the use of power-efficient methodologies as well as techniques that require a lesser number of transistors. In this paper, a magnitude comparator is developed using full adder design logic. Full adders are basic components of the ALU which is the logical and arithmetical unit of the microprocessors and Digital Signal Processing (DSP). This design consumes less power and area when compared to other logic styles in the literature. The proposed comparator has been designed using DSCH 3.5 and simulations are done on Microwind 3.5 via 0.12 μ technologies. This comparator shows a power consumption of 31.746μW using 36 transistors. The proposed design exhibits a full adder logic-based comparator with less power consumption and transistor count as compared to those in recent literature.