Design and prototyping of an E1 Drop_Insert soft core

Abstract

The paper describes the design and prototyping of a telecommunication intellectual property soft core developed in the scope of an industry–academia co-operation. The soft core allows the manipulation of E1 2048 kHz 32-channel carrier information. It inserts/removes data into/from an E1 frame and multiframe structures. The soft core was fully described in VHDL, functionally validated by simulation, prototyped in FPGA platforms and certified using E1 testers. The main use of the developed soft core in the implementation of data communication equipment is to allow multiple users to share a common E1 carrier with a flexible scheme for bandwidth allocation. The main contribution of the paper is a reusable hardware module that increases performance and reduces latency of the data treatment when compared to existing commercial solutions.