Performance Driven FPGA Design Analysis with ASIC Perspective of Vector Quantization

Abstract

The paper presents and analysis two different approaches for the design of modular and optimized Vector Quantisation (VQ) architectural blocks for the generation of the winner Index from a set of Code vectors giving the best match to the input image vector. The two proposed methods are then analysed for area, logical and routing delays and the ease of redesign to suit specific requirements on the FPGA platform. If an FPGA design need be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC porting will be efficient. The structured and hierarchically design of VQ lead to the consideration of the dedicated parallel architectures in two ways, in the direction of Codebook size ‘N’ and the vector dimension ‘K’, that process with high efficiency. Flexibility in terms of Codebook size expansion and Input vector dimension makes the new design fast to re-configure and meet the specific and challenging needs of a single functioned, tightly constrained and real time VQ encoder. The soft IP core design was targeted on to Xilinx Virtex-5. Simulation result analyses indicate that the design with parallelism only in the direction of the codebook size ‘N’ gives the desirable performance and is cost effective even for an ASIC implementation performed in Cadence tool. The design satisfies the performance requirements of for a real time image processing. Reconfiguring the codebook size and vector dimension makes redesign simpler to suit applications requirements but at the cost of re-synthesis and is capable of even multiplexed image transmission due to reduction in the Bandwidth