Design and performance of a new flash EEPROM on SOI(SIMOX) substrates

Abstract

A new flash EEPROM cell and a novel erasing scheme on SOI substrates are reported. This flash EEPROM cell incorporates two separate control gates, located an opposite sides of the silicon film. One is a conventional control gate fabricated on top of the film as in bulk cells. The second control gate is the back gate itself, which is located underneath the silicon film and is inherent to all SOI MOSFET structures. As usual, the front control gate is used to WRITE the cell. By contrast, the back control gate is used to ERASE the cell in a new erasing scheme arrangement. In this scheme the back gate and the drain are used to invert the back channel and operate it in the impact ionization regime, such as to produce electron/hole pairs. Most of the generated electrons flow into the drain and some are injected into the back (buried) oxide. The holes, however, are accelerated towards the front gate, and many are finally injected into the floating gate, sandwiched between the front gate dioxide and front control gate. A prototype flash EEPROM cell was fabricated using a standard 1-metal, 1-poly CMOS SOI process and tested for concept proof. The cell was programmed via avalanche channel hot-electron injection from the drain pinch-off region, same as in bulk cells.