Design and Performance Analysis of 6T SRAM Cell in 22nm CMOS and FINFET Technology Nodes

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In modern day VLSI system design memories are the vital blocks and they need to be thoroughly investigated with respect to area, power and performance before their fabrication. SRAM cell is an important candidate in the design of memories and a significant amount of attention is being paid to its design due to the ever increasing demand in data handling. The submicron scaling of conventional CMOS devices affect their performance due to short channel effects and circuits become unreliable. Further below the sub-32nm regime, FinFETs are proposed to be the best possible substitutes for CMOS technology. In this paper, we have designed and analyzed the performance of CMOS and FinFET based 6T SRAM cells at 22nm technology and compared the performance metrics of SRAM cell. The design infers that while both the circuits offer stable SNM at a power supply of 1 V, the FinFET based SRAM cell yields superior read and write performances due to its high process variation tolerance.