Abstract
In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness T si (20nm); gate oxide thickness T ox (3nm); buried oxide thickness T box (200nm) and gate length L G (60nm). So that maintaining a subthreshold factor, the on/off current ratio, threshold voltage (V th = 0.5V) and drain induced barrier lowering for a given gate length L G . Analog performance of device has been investigated interns of g m , g ds , A v , f t and f max . All these results have been simulated by using SILVACO TCAD Keywords: Index Terms: DG-SOI-MOSFETs, DIBL, and Threshold voltage
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