Abstract
In this paper, the impact of process parameters namely gate length (L), thickness of silicon film (Tsi) and gate oxide thickness (Tox) with increased well bias on the electrical parameters viz., drain current (ID), threshold voltage (VT), subthreshold slope (SS) and drain induced barrier lowering (DIBL) of a short-channel bulk planer junctionless transistor (BPJLT) are systematically investigated with the help of extensive device simulations. The effect of positive well bias is utilized to improve the hot carrier effect of a BPJLT. The effect of well doping concentration on threshold voltage is studied. The threshold voltage variations with respect to well bias for different temperatures are studied.
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