Abstract
Nano electronic single electron transistor is an emerging candidate for replacing the conventional Complementary metal oxide Semiconductor devices for computing systems. Single Electron Tunneling is a promising technology, which offers greater scaling potential than Metal oxide semiconductor and it consume ultra low power. This paper investigates reconfiguration of Single Electron Encoded threshold logic gate from the logic design perspective for implementing addition and subtraction operation. A thorough analysis on computational unit has been performed and its performance in terms of area, delay and power consumption has been estimated and its suitability for higher end processing also has been evaluated.
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