Design and Testing of Digital Logic Gates Using HCS Macro-Model

Abstract

Single Electron Transistor (SET) has become very popular in industry as well as in academia. As SET can control the tunneling of electrons one by one through the channel so that power dissipation is very low as compared to conventional Complementary Metal Oxide Semiconductor (CMOS), though it has high speed, high gain like properties. So, the hybridization of CMOS with SETcan be used in modern Very Large Scale Integration (VLSI) circuit design, and this technique is very popular as Hybrid CMOS–SET (HCS) which uses less power with high speed of response. But the model requires two distinct simulators, such as, Simulation Program with Integrated Circuit Emphasis (SPICE) for CMOS and SIMON or Korea Single Electron Circuit Simulator (KOSEC) or Monte Carlo Single Electronics Simulator (MOSEC) or Single-Electron Nano Electronic Circuit Analyzer (SENECA) for SET, to simulate a single HCS model. To overcome this problem of HCS, macro- modelling of SET has been introduced by different researchers which can be simulated by using MATLAB with SIMULINK, SPICE and so on. In this present paper, macro model of SET has been incorporated with CMOS so that it can be simulated using a single software and this technique has been used to develop different logic circuits and the output can be controlled by the individual components of SET macro model. The simulation results show that the proposed model also consumes low power (0.275 nW to 0.55 nW) with high speed which can be used in VLSI design.