Design and Implementation of Multi-bit Self-checking Carry Select Adder

Abstract

This paper focuses on the design of self-checking carry select adder (CSTA) using FinFET devices. The CSTA adder comprises of Boolean to Excess-1 converter and D-latch. While going for multi-bit addition, it is more prone to various types of faults. Hence, the design of a self-checking CSTA is more prone to faults. This paper focuses on the design of 4-bit CSTA using FinFET and a sum bit checker design using FinFETs. The simulations are carried out using Cadence® Virtuoso platform with 32-nm FinFET technology library. The results demonstrate a device overhead of 12 and slight increase in delay and power consumption. However, the purpose of the carry checker design has a great impact on preventing the propagation of faults and ultimately ends in fault-free circuit.