Design and Implementation of Modified Distributive Arithmetic Based DWT Architecture Using FPGA

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This paper presents a modified distributive arithmetic based DWT architecture and is implemented in FPGA. The modified DA-DWT architecture has a latency of 44 clock cycles and a throughput of 4 clock cycles. This design is twice faster than the reference design and is thus suitable for applications that require high speed image processing algorithms. In this paper, reliable and high speed DWT architecture is designed and implemented in FPGA which can be used as a co-processor for image compression and decompression. The bi-orthogonal wavelets, with different number of coefficients in the low pass and high pass filters, increase the number of operations and the complexity of the design, but they have better SNR than the orthogonal filters. The code has been written in VHDL and implemented on the FPGA using a 32 x 32 random image. This architecture enables fast computation of DWT with parallel processing. It has low memory requirements and consumes low power. This architecture is faster than the existing architectures as the latency is reduced by half clock cycles and through put is increased by a factor of 2.