Design and implementation of low power and high performance network interface for 2×2 SDM based NoC

Abstract

As VLSI technology growing exponentially, silicon chips can accommodates more cores on chip this will lead to very high computational power but poor communication among on-chip processors and memory. To overcome this we proposed spatial division multiplexing based network-on-chip with modified network interface. Proposed network interface provide high throughput with optimized area and consume very low power. We have evaluated proposed SDM based NoC (Network-On-Chip) with high performance network interface for 2×2 network which occupied only 4% of resources on Xilinx spartan6 SP605 FPGA. We modeled the network interface using VHDL and multicore platform is prepared by using Xilinx EDK and verified computationally complex application at 88.6MHz processor frequency but achieved high throughput.