Design and Implementation of a High-Speed Reconfigurable Feedback Shift Register

Abstract

A high-performance and dynamic reconfigurable feedback shift register is presented, which provides full support to linear and nonlinear feedback shift register. The architecture can be also reconfigured any lengths, feedback taps and feedback function. To save the hardware cost and get shorter critical path, we proposed EXCLUSIVE-OR tree network to implement linear feedback function, and put forward AND-OR tree network to optimize nonlinear feedback function. The design has been realized using Altera's FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18 mum CMOS process. The result proves that the propagation time of reconfigurable feedback shift register with 256 lengths is 3.28ns. Compared with other designs, the architecture can achieve relatively high flexibility, furthermore, it has an obvious advantage in the aspect of speed.