Test Pattern Generation using NLFSR for Detecting Single Stuck-at Faults

Abstract

The generation of test patterns for the detection of faults in VLSI circuits is the most integral part of fault detection. The patterns are generated using Pseudorandom Number Generator (PRNG) and applied to the circuits. The most commonly used PRNG is Linear Feedback Shift Register (LFSR). Other than LFSR, Non-Linear Feedback Shift Registers (NLFSR) can also be used as pattern generator. This paper mainly focuses on the advantages of using NLFSRs over ATPG. It compares the fault coverage of single stuck-at faults using NLFSR technique with the fault coverage of single stuck-at faults using ATPG tool for few ISCAS’89 circuits. This paper also shows the reduction in terms of total on-chip power while using NLFSR as pattern generator instead of LFSR. The netlist generation of the circuits is done by using Synopsys Design Compiler tool and ATPG is achieved using Synopsys TetraMax tool. In the NLFSR technique, faults are injected manually and patterns are added to the CUT to get the fault coverage. The faults injected in the circuits are detected in the simulation results of the faulty circuit. The NLFSRs and LFSRs are designed using Xilinx Vivado. The comparison between the fault coverage and power consumption of the techniques are shown in a tabular form and the simulation results for NLFSR technique is shown. It is observed that while the ATPG does not yield 100% fault coverage, NLFSR technique gives 100% coverage. The difference in on-chip power between LFSR and NLFSR is also found to be very large with NLFSR consuming more than 80% less power than LFSR.