Design and implementation of a fully differential 2nd‐order CIFF DSM with the synthetic techniques of novel CDS chopper‐integrator and DER using additive‐error capacitors

Abstract

SummaryCompared to the independent application of chopper stabilization or correlated double sampling (CDS), this paper proposed a 2nd‐order cascade of integrators with feedforward delta–sigma modulator (DSM) utilizing an innovatively synthetic technique of chopper‐integrator within CDS at 1st stage for reducing the flicker noise and DC offset cancelation from about 9.5 mV to −4.4 μV ± 115.6 μV (δ). On the regard of further enhancing the noise suppression and mitigating the nonlinearities of capacitor mismatch, instead of applying the dynamic elements randomization (DER) to the nonlinear correction of DAC under multi‐bits quantizer, here the operation of 3‐bits DER with scrambler has been intelligently employed on the 2nd integrators' sampling capacitors to gain the 2nd noise‐shaping characteristic in spite of 1‐bit quantizer. The noise floor could be theoretically scaled down by −16.1 dB at input frequency of 10 kHz within the limited bandwidth of 100 kHz. The prototype DSM was manufactured in 180‐nm BCD process with an active area of 0.2625 mm2 and achieves the SNDR‐based Schreier figure‐of‐merit (FoMS) of 144 dB and Walden figure‐of‐merit (FoMW) of 25.96 pJ/conv under a 3.3 V supply at 10 kHz working frequency.