Abstract
This paper proposes an accurate analysis of the settling error in a Correlated Double Sampling (CDS) Integrator. This analysis is done in time domain and its MATLAB (M type) file implementation is directly applicable to the faster design implementation of Switched Capacitor (SC) based Sigma Delta (ΣΔ) Modulators. The analysis of settling error is done during the integration and sampling phase of a CDS Integrator. Validation of the proposed analytical model is done via extensive behavioral and transistor level simulations of a SC based Second Order ΣΔ Modulator employing a CDS integrator, in MATLAB and HSPICE, respectively, with Tower 0.18 µm process model parameters. The simulations were performed at two different values of modulator sampling frequency of 655 KHz and 5.24 MHz. The simulation results show a close agreement between the HSPICE simulations and proposed analytical model.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
