Design and Implementation of a Deep Learning Target Detection System

Abstract

Target detection is a research hotspot in the field of computer vision. It has a very broad application prospect in intelligent transportation, intelligent video surveillance, aerospace and many other fields. At present, target detection based on convolutional neural network has absolute advantages over the traditional target detection algorithm. However, due to the complexity of the convolutional neural network structure and the large amount of calculation, it is difficult to achieve real-time application in the embedded platform with insufficient resources and low power consumption. As one of the best real-time target detection models, YOLOv2-Tiny has simple structure and fast detection speed. Compared with other convolutional neural network models, YOLOv2-Tiny is more suitable for low-power embedded platform. In addition, by analyzing the advantages and disadvantages of GPU, ASIC and FPGA in power consumption and price, the zynq-7020 embedded platform based on ARM + FPGA hardware architecture is selected to design and implement the target detection system based on YOLOv2-Tiny. The experimental results show that the network with more feature scales has a significant improvement on the detection and recognition of small targets. Finally, the FPGA verification system is designed, and a high-performance hardware acceleration scheme of convolution neural network is realized by using the parallelism within convolution neural nodes, the parallelism between convolution neural nodes and the reuse of feature parameters. Finally, the data transmission and receiving of each convolution layer is realized on the embedded hardware system, and the verification of target detection and recognition algorithm is completed. The convolution neural network accelerator designed in this paper achieves the effective computing power of 24.86 GOPs and the power consumption ratio of 11.69 GOPs /W on Zynq-XC7Z020 FPGA.The detection rate is 3.4 frames per second. The algorithm and its hardware verification system designed in this paper have the characteristics of good accuracy, small platform size and high resource utilization, which can provide reference for the embedded scheme of neural network.