Design and FPGA Implementation of Digital Frequency Modulation Receiver

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In this paper, we introduce the design of a digital frequency modulation receiver using FPGA. The main component in the design is digital phase locked loop (DPLL) which compensate any changes between the frequency and phase of the input modulated signal and the frequency and phase of numerically controlled oscillator. The input to the receiver is 8-bit represents the sampled discrete time signal from the analog modulated received frequency modulation signal. The receiver is designed using Xilinx system generator and implemented on the FPGA board (Xilinx Vitrex-7 XC7VX550t board), works with 350 MHz and consumes 120 mW.