Design and fabrication of high aspect ratio fine pitch interconnects for wafer level packaging

Abstract

The Packaging Research Center (PRC) at Georgia Tech has been exploring and evaluating novel compliant nano interconnect designs to enable high density I/O architecture for the next generation chip assembly. Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. We propose high aspect ratio interconnects as a solution that can support both electrical and mechanical requirements. The fabrication of these interconnects is similar to the standard IC fabrication and involves only one additional step beyond the standard CMOS wafer processing, thus making it a cost effective wafer level process. Extensive modeling was carried out to design 40 /spl mu/m pitch interconnects with optimized electrical and mechanical properties. The fabrication of fine-pitch copper interconnects with aspect ratio of 1:5 was demonstrated as a low-cost wafer level process. Results show that these interconnects provide the optimal combination of electrical and mechanical requirements and hence provides a viable solution for next-generation electronic packaging that can support extremely high I/O density.