Fabrication of High Aspect Ratio 35 /spl mu/m Pitch Interconnects for Next Generation 3-D Wafer-Level Packaging by Through-Wafer Copper Electroplating

Abstract

3-D wafer level packaging is one of the key technologies to fabricate next generation compact, highly dense and high speed electronic devices. In order to realize these future nanoscale IC devices, fabrication of through-wafer interconnects with ultra fine pitch, is the foremost requirement. High aspect ratio through-wafer interconnects connect several devices in vertical axis and thus offer the shortest possible interconnection length. Due to the shortest interconnect length, parasitic losses and time delay during signal propagation is the minimum, which result in faster speed. In this paper, we report the fabrication of very high aspect ratio (/spl sim/15) ultra fine pitch (-35 /spl mu/m) through-wafer copper interconnects by innovative electroplating process. In this technique, process parameters are continuously varied as the electroplating process goes on. To reduce the chances of void formation and to ensure the complete wetting of via surface with copper electrolyte, hydrophilic nature of vias surface is increased. Copper interconnects having diameter as low as 15 /spl mu/m and height as high as 400 /spl mu/m have been fabricated by above technique. Vertically standing and smooth copper interconnects with very fine grains are obtained, which are characterized by SEM.