Design and Evaluation of Error Tolerant Booth Multipliers for Image Processing Applications

Abstract

The emergence of approximate computing has aided digital integrated circuits in the path towards power saving, better performance, and reduced circuit complexity at the cost of reduced accuracy. In this paper, 8-bit approximate booth multipliers have been proposed using i) Approximate radix-4 Booth Encoders (ABE), ii) truncated partial products and iii) recursive Carry Look Ahead (CLA) adder for final addition to generate the final product terms. The accuracy of the multiplier is scaled by introducing approximation factor in terms of truncation and utilization of ABEs. State of Art accurate booth multiplier is also implemented for comparison purpose. Error performance of the proposed multipliers has been evaluated by means of Normalized Mean Error Distance (NMED). To show the feasibility of employing approximate circuits for real time applications, image multiplication using approximate booth multipliers have been realized. The performance of each of the multipliers is demonstrated by measuring PSNR and SSIM and compared using an image processing application. Simulations using the approximate multipliers show that the proposed approximate multipliers have reduced power consumption and area compared to the existing multipliers. All the circuits have been simulated using 180nm CMOS technology library.