Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects

Abstract

The work presents a configurable network interface (NI) macrocell to be integrated in Spidergon network-on-chip (NoC) infrastructures, and addresses the problem of its functional verification. The NI architecture supports multiple native bus for the IP cells connected to the NoC and the conversion of data size, protocol and frequency between the NoC and each IP. Differently from many state-of-art NI designs the proposed macrocell features also the hardware implementation of advanced networking features such as security, order handling, error management, store and forward transmission, memory remapping, power management. Such a configurable and complex design poses several challenges in terms of functional verification. Direct HDL testbenches fails covering corner cases and typically are based on handwritten testbenches that are error-prone. In formal methods the verification engineer tries to extract deterministic laws/relationships internal to the HDL description, and then to prove theorems to check the netlist functional behavior. However in complex designs the state explosion problem limits model checking, and the cost of theorem proving becomes prohibitive because of the amount of skilled manual guidance it requires. To overcome such issues a constrained-random coverage-driven approach is presented and customized to be applied to the novel NI as design under test (DUT). Starting from DUT specifications, a software verification platform is created performing these tasks: generating traffic patterns which are constrained-random, i.e. random within variations ranges specified by the user; monitoring the DUT outputs and checking them according to pre-programmed rules; parsing collected outputs into a functional coverage scheme to check if all possible cases have been stressed and covered by the tests. This enables a coverage-driven verification: the user continues developing and running tests until there are no holes left in the coverage plan. As result of this verification strategy full code and functional coverage is achieved. Implementation results of the verified NI core in 45 nm and 65 nm CMOS technologies are also provided and compared to state-of-art NI designs.