Network on chip design and implementation on FPGA with advanced hardware and networking functionalities

Abstract

As there is a rapid growth in use of consumer embedded products from past decade, new tendencies forecast highly the usage of heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. As MPSoCs are made up of hundreds of cores, Intercommunication requirements will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, and the different components are designed by various vendors, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products. To overcome the above said problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. However, the development of application-specific NoCs for MPSoCs is a complex engineering process that involves the definition of suitable protocols and topologies of switches, and which demands adequate design flows to minimize design time and effort. In fact, the development of suitable high-level design and synthesis tools for NoC-based interconnects is a key element to benefit from NoC-based interconnects design in nanometer-scale CMOS technologies. This paper presents the design and implementation of FPGA based Network on chip (NoC) which is scalable packet switched architecture with advanced Networking functionalities such as store & forward transmission, error management, power management and security. All these features are built on basic NI core, which includes data packetization/depacketisation, frequency conversion, data size conversion and conversion of protocols with limited circuit complexity and cost.