Design and Comparison of Advanced Low Power SRAM Cells using GNRFET Technology

Abstract

The static random access memory (SRAM) Array is used in applications such as cache memories, microprocessors, and portable devices such as smart watches and mobile phones. As technology advances to the submicron level, power dissipation becomes a major disadvantage in SRAM cells, necessitating the development of low-power applications. As a result, it's important to design a memory that consumes less power. The main motive of this paper is to design 4*4, 8*8, and 16*16 SRAM array using 6T and 7T SRAM cells using Graphene Nano Ribbon Field Effect Transistor (GNRFET) technology and compare power dissipation between Complementary Metal Oxide Semiconductor (CMOS) and GNRFET technologies. The MOS-GNRFET HSPICE libraries in HSPICE TOOL is used to perform transient analysis for the Read and Write operations.