Design and analysis of VLSI-based arithmetic arrays with error correction

Abstract

An alternative fault-tolerant design for VLSI-based arithmetic arrays using the partitioning technique is presented in this paper. The basic concept behind this study is that the arithmetic array can be divided into m parts and its operation can be completed through m iterative calculations with one part. By taking three such parts with a majority-voting technique at each iteration, error correction can be achieved through m-step computations. This leads to the same capability of fault tolerance as triple modular redundancy (TMR). The overheads of chip area and operation time are only introduced by multiplexers, latches and voters, and can be reduced by selecting an appropriate value m. Based on the AT2 measure of VLSI performance (where A is denoted by the chip area and T is the operation time), the proposed design is shown to be superior to the general TMR method. In addition, some application-specific trade-offs between speed performance and area cost are presented.