Abstract
This paper reports design and analysis of new low triggering voltage dual-polarity silicon-controlled rectifier (SCR) ESD protection structures and circuits in CMOS. Design optimization technique enables flexible ESD triggering voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</sub> ), ESD holding voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> ) and ESD protection capability. Measurements show very low and adjustable V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</sub> , low leakage (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">leak</sub> ), low noise figure (NF), low ESD-induced parasitic capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ESD</sub> ) and fast ESD triggering time (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ). It achieves high ESD protection to Si ratio of ESDV~6.83V/ μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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